Jay: A New Open-Source Shader Compiler Being Developed For Intel GPUs
Jay: A New Open-Source Shader Compiler Being Developed For Intel GPUs
https://www.phoronix.com/news/Intel-Jay-Mesa-Shader-Compiler
Publish Date: 2026-04-07 17:32:00
Source Domain: www.phoronix.com
Jay is a new open-source shader compiler being developed for Intel’s open-source OpenGL and Vulkan Linux drivers. Ultimately this Jay shader compiler should help in delivering better Linux graphics performance with modern Intel hardware.
Last year Alyssa Rosenzweig joined Intel who led work with Asahi Linux on their AGX graphics driver code and was a contractor as well for Valve working on the Linux graphics stack. With Rosenzweig’s contributions to Mesa over the years was a lot of work on shader compilation and NIR, so to not much surprise now, she’s been leading work on a new Intel shader compiler.
Though it is a bit surprising to see Jay being developed as besides the “BRW” shader compiler long used by Intel drivers within Mesa, Intel also has the Intel Graphics Compiler (IGC) used by their Compute Runtime for OpenCL and Level Zero on Linux. IGC is also used on Microsoft Windows not only for compute but also their graphics shader compiler too. I was previously told a few years ago that Intel was looking at using IGC for their Mesa drivers, but now it turns out there is a new solution being developed with this “Jay” compiler.
In today’s Mesa merge request introducing Jay, Alyssa explained:
“This MR adds Jay, a new SSA-based compiler for Intel GPUs. This is an early work-in-progress. It isn’t ready to ship, but we’d like to move development in-tree rather than rebasing the world every week. Please don’t bother testing yet – we know the status and we’re working on it!
Jay’s design is similar to other modern NIR backends, particularly ACO, NAK and AGX. It is fully SSA, deconstructing phis after RA. We use a Colombet register allocator similar to NAK, allowing us to handle Intel’s complex register regioning restrictions in a straightforward way. Spilling logical registers is straightforward with Braun-Hack… but how we apply the standard SSA backend design to Intel hardware is not. You can read the code if you’re curious, but I plan to “spill” the beans at…